The invention relates to semiconductor device assemblies, and more particularly to techniques for analyzing and debugging circuitry associated with a flip-chip bonded integrated circuit.
In recent years, the semiconductor industry has seen tremendous advances in technology that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
There have been a number of semiconductor packaging types used to increase the number of pad sites available for a die and to address other problems. One increasingly popular packaging technique is called controlled collapse chip connection or flip-chip packaging. In this technology, the bonding pads are provided with metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads and soldered. As a result, the dies are often referred to as xe2x80x9cflip-chipxe2x80x9d devices. Each bump connects to a corresponding package inner lead. The packages that result are lower profile and have lower electrical resistance and a shortened electrical path.
The output terminals of such packages vary, depending on the package type. For example, some output terminals are ball-shaped conductive bump contacts (usually solder, or other similar conductive material), and they are typically disposed in a rectangular array. These packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA). Another type of package, commonly known as pin grid array (PGA) package, implements the output terminals as pins.
Once the die is attached to the package, the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer from which the die is singulated. The portion of the die that includes the epitaxial layer, which contains the transistors and other active circuitry, is often referred to as the circuit side of the die or the front side of the die. The circuit side of the die is positioned very near the package, and opposes the back side of the die. Between the back side and the circuit side of the die is single crystalline silicon.
The positioning of the circuit side provides many of the advantages of the flip-chip device. However, in some instances the orientation of the die with the circuit side face down on a substrate may be a disadvantage or present new challenges. When a circuit fails, when circuit testing is desired, or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side is obtained only from the back side of the chip. This is challenging since the transistors are in a very thin layer (e.g., about 10 micrometers) of silicon buried under the bulk silicon (e.g., greater than 500 micrometers). Thus, the circuit side of the flip-chip die is not visible or accessible for viewing using optical or scanning electron microscopy.
Although the circuit of the integrated circuit (IC) is buried under the bulk silicon, infrared (IR, hereinafter including both IR and also near-infrared (nIR) where the wavelength is between 800 and 2000 nm) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than about 200 microns in order to view the circuit using IR microscopy. To illustrate this difficulty, on a die that is 725 microns thick, this means removing (or thinning) at least 625 microns of silicon before IR microscopy can be used.
Thinning a flip-chip bonded die for failure analysis can be time consuming and burdensome. According to one common approach, thinning is accomplished in two or three steps. First, the die is thinned across the whole die surface. This is also referred to as global thinning. Global thinning is done to allow viewing of the active circuit from the back side of the die using IR microscopy. Mechanical polishing is one method for global thinning. Mechanical polishing can be done keeping the surface fairly flat across the die surface. This process can also produce very smooth surfaces to obtain clear images using IR (including nIR) microscopy. Too high a surface roughness causes scattering of illumination light and the reflected light from the surface being imaged. Once an area is identified as an area of interest and it is determined that access is needed to a particular area of the circuit, local thinning techniques can be used to thin an area smaller than the die size. Laser microchemical etching of silicon is one method of local thinning.
A particular problem is encountered attempting to image the circuit beneath the trench surface created by laser chemical etching (LCE). In laser chemical etching, a focussed laser beam is scanned over a small area on the silicon surface of the die in the presence of chlorine gas. The focussed laser beam is absorbed in silicon and the surface gets heated to a very high temperature. The heat caused by the laser beam is generally high enough to cause melting of the silicon surface. The chlorine gas reacts with the hot silicon surface or molten silicon and forms volatile silicon chloride. The unreacted molten silicon re-crystallizes and forms the silicon surface. Although this process produces fairly smooth surfaces, the surface resulting after LCE destroys the imaging process.
The surface resulting after laser chemical etching is found to have crystal defects using TEM (Transmission Electron Microscopy) mainly dislocations and threading defects which are not present in the starting material. These crystal defects serve as scattering centers for light and are believed to be the cause for the imaging problems. Additionally the surface formed in the LCE process causes some degree of amorphization (the surface being composed of very small size grains) of silicon.
The present invention is directed to imaging circuit regions through a silicon surface that was impaired by thinning. In connection with the present invention, it has been discovered that impairment by crystal defects can be overcome for circuit-viewing by laser-thermal annealing. Such annealing is useful in overcoming crystal-defect impairment as caused by multiple types of thinning processes.
According to one example embodiment, the back side of a semiconductor device, such as a flip-chip semiconductor device, is thinned to expose a selected region in the substrate. An imaging path is then provided through the back side of a semiconductor device for subsequently obtaining an image of circuitry as viewed from the back side. The imaging path can be provided using any of various mechanisms including, for example, conventional global and local thinning techniques. Specifically, silicon thinning that uses a laser chemical etching process results in the formation of crystal defects that inhibit the ability to obtain images through the back side of the semiconductor device. This problem is addressed by a combination of a surface smoothing process and an annealing step to reduce the crystal defects in silicon. The present invention overcomes this problem by reducing, e.g., smoothing, the crystal defects.
In a more particular embodiment, the imaging path is provided by thinning via laser-chemical etching the back side of the semiconductor device under a pressure exceeding a threshold level, and then reducing the pressure to a level below the threshold level and scanning the back side of the semiconductor device using a laser. IR microscopy is then used to capture an image of a circuit in the circuit side of the semiconductor device through the back side of the semiconductor device.
In another example embodiment, the present invention is directed to a system for providing an imaging path for imaging through the back side of a semiconductor device to its circuit side. The system includes: a laser-chemical etching arrangement including a laser-chemical etcher configured and arranged to apply a high temperature to the back side of the semiconductor device and to thin the back side at a first energy level, the laser-chemical etching arrangement further including an adjustment to use the laser-chemical etcher for scanning the back side of the semiconductor device in the imaging path and at an energy level that is less than the first energy level and for reducing crystal defects in the imaging path; and a microscopy arrangement configured and arranged to apply light through the imaging path and to obtain images of circuitry in the circuit side of the semiconductor device. In a more particular example embodiment, the system further includes a gas chamber and the adjustment is configured and arranged to change pressures within the chamber from a first pressure in excess of about one milli-Torr to a second pressure that is less than about one milli-Torr.
According to another example embodiment, the back side of a die is globally thinned via plasma etching, and crystal defects resulting therefrom are overcome for viewing underlying circuit material by laser-thermal annealing.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.